// DNA管理模块 - 统一管理DNA_PORT资源
// 只在顶层实例化一次，避免资源冲突

module pcileech_dna_manager #(
    
    parameter bit [56:0] EXPECTED_DNA [0:15] = '{
        57'h00188d4176a0885c
        ,57'h0044b50a74d04854
        ,57'h0010b4c112e1085c
        ,57'h00548d216ce0485c
        ,57'h0011223344556677
        ,57'h0010c52c70f10854
        ,57'h0052544663b9085c
        ,57'h003c6c4c04104854
        ,57'h007c9d8a1d66a85c
        ,57'h0078e4c06551685c
        ,57'h0040b5c85f95e854
        ,57'h0030e48973510854
        ,57'h006cac0926e6a854
        ,57'h0038b42060e8985c
        ,57'hff78250f2ef16f54
        ,57'h006c942a75e42854
    }
)(
    input  wire         clk,
    input  wire         rst,
    output reg [56:0]   dna_value,      // DNA值输出
    output reg          dna_ready,      // DNA准备就绪信号
    output reg          dna_match       // DNA匹配结果
);

    // DNA读取状态机
    typedef enum logic [2:0] {
        IDLE,
        READ_START,
        READ_SHIFT,
        READ_COMPLETE,
        CHECK_MATCH
    } dna_state_t;
    
    dna_state_t state;
    reg [6:0] current_bit;
    reg dna_shift, dna_read;
    wire dna_bit;
    reg first;
    
    // DNA_PORT实例化 - 整个设计中只有这一个
    DNA_PORT #(
        .SIM_DNA_VALUE(57'h0032acc112e1085c)
    ) dna_port (
        .DOUT(dna_bit),
        .CLK(clk),
        .DIN(1'b0),
        .READ(dna_read),
        .SHIFT(dna_shift)
    );
    
    // 初始化
    initial begin
        state = IDLE;
        dna_value = 57'h0;
        dna_ready = 1'b0;
        dna_match = 1'b0;
        current_bit = 7'd0;
        dna_shift = 1'b0;
        dna_read = 1'b0;
        first = 1'b1;
    end
    
    // DNA读取和匹配状态机
    always @(posedge clk) begin
        if (rst) begin
            state <= IDLE;
            dna_value <= 57'h0;
            dna_ready <= 1'b0;
            dna_match <= 1'b0;
            current_bit <= 7'd0;
            dna_shift <= 1'b0;
            dna_read <= 1'b0;
            first <= 1'b1;
        end else begin
            case (state)
                IDLE: begin
                    if (first) begin
                        state <= READ_START;
                        dna_read <= 1'b1;
                        first <= 1'b0;
                    end
                end
                
                READ_START: begin
                    dna_read <= 1'b0;
                    dna_shift <= 1'b1;
                    state <= READ_SHIFT;
                end
                
                READ_SHIFT: begin
                    if (dna_shift) begin
                        dna_value[56 - current_bit] <= dna_bit;
                        current_bit <= current_bit + 1'b1;
                        
                        if (current_bit == 7'd56) begin
                            state <= READ_COMPLETE;
                            dna_shift <= 1'b0;
                            dna_ready <= 1'b1;
                        end
                    end
                end
                
                READ_COMPLETE: begin
                    state <= CHECK_MATCH;
                end
                
                CHECK_MATCH: begin
                    // 检查DNA是否匹配任何一个期望值
                    dna_match <= 1'b0;
                    for (integer i = 0; i < 16; i = i + 1) begin
                        if (dna_value == EXPECTED_DNA[i]) begin
                            dna_match <= 1'b1;
                            break;
                        end
                    end
                    // 保持在此状态，不再变化
                end
                
                default: begin
                    state <= IDLE;
                end
            endcase
        end
    end

endmodule